| Apr 17, 2026 | Enhancing Instruction Prefetching via Cache and TLB Management accepted at ISCA 2026. |
| Mar 20, 2026 | I will serve as a reviewer in the Program Committee of the ISCA 2026 Artifact Evaluation. |
| Jun 25, 2025 |  Patent Published: “Perceptron-based off-chip predictor” (EP4575807A1) Filed in December 2023 – now publicly available via EPO. Combines off-chip perceptron prediction with adaptive prefetch filtering for memory systems.  View Patent |  Download PDF. |
| May 06, 2025 | I served as a reviewer for the 12th International BSC Severo Ochoa Doctoral Symposium 2025. |
| Jan 20, 2025 | I attended the HiPEAC 2025 Conference in Barcelona, Spain. |
| Nov 16, 2024 | Following the end of my Doctoral Studies, I was promoted to AI4S Fellow Recognized Researcher. |
| Sep 27, 2024 | Successfully defended my PhD thesis entitle: “Interaction Between Computer Architecture and Artificial Intelligence” and received Cum Laude. |
| May 30, 2024 | Presented Practically tackling memory bottlenecks of graph-processing workloads at IPDPS 2024 in San Francisco, California, United States of America. |
| Mar 05, 2024 | Presented A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering at HPCA 2024 in Edinburgh, United Kingdom. |
| Jan 17, 2024 | A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering received the HiPEAC 2024 Paper Award. |
| Dec 18, 2023 | Practically tackling memory bottlenecks of graph-processing workloads accepted at IPDPS 2024. |
| Oct 31, 2023 | A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering accepted at HPCA 2024. |
| Aug 24, 2020 | Characterizing the impact of last-level cache replacement policies on big-data workloads accepted at IISWC 2020. |