Collaborators
Marc Casas is a technical research lead at the Barcelona Supercomputing Center (BSC) and lecturer at the Universitat Politècnica de Catalunya (UPC). His research lays between parallel computing (e.g., sparse linear algebra, parallel deep learning) and computer architecture (e.g., memory address translation, vector architectures). He is the technical lead of the SONAR (parallel SOftware and New ARchitectures) research group, composed of PhD students, engineers, and postdocs. Marc has led BSC contributions to several european projects (Mont-Blanc2020, European Processor Initiative, etc.), and research collaborations with Intel and IBM.
Marc has been at BSC since 2013. He was a postdoctoral research scholar at the Lawrence Livermore National Laboratory (LLNL) from 2010 to 2013. He received the Marie Curie and Ramón y Cajal Fellowships in 2014 and 2018, respectively. He obtained a 5-years degree in mathematics in 2004, and a PhD degree in Computer Science in 2010 from the Universitat Politècnica de Catalunya (UPC).
Georgios (Yorgos) Vavouliotis is a Senior Researcher at the Huawei Research Center in Zurich. He earned his Ph.D. from Universitat Politècnica de Catalunya and the Barcelona Supercomputing Center, and holds a diploma in Electrical and Computer Engineering from the National Technical University of Athens.
His research explores the frontiers of computer architecture, pioneering innovative microarchitectural solutions to address critical computational challenges. Key areas of focus include advanced techniques for reducing address translation overheads, enhancing cache prefetching performance, and developing smart cache and memory management strategies for complex computing environments. By leveraging AI and machine learning techniques, he builds intelligent, adaptive components while rethinking microarchitectural designs for emerging application domains.
Vavouliotis’s work has been recognized with Best Paper and Best Poster awards and has been featured primarily in top-tier computer architecture conferences, including ISCA, HPCA, MICRO, and ASPLOS.
Martí Torrents is a computer architecture researcher with over seven years of experience spanning both academia and industry. His research interests lie at the intersection of hardware and software optimization, with specific expertise in high-performance networks, operating systems, networks-on-chip, and shared memory systems. His work extensively explores variation-aware architectures, hybrid hardware-software designs, and advanced hardware and software prefetching mechanisms. He possesses strong system-level programming skills, particularly in full-system simulation environments such as gem5. His research during his master’s and doctoral studies has resulted in seven publications in peer-reviewed journals and international conference proceedings, as well as a patent filed during his tenure at Intel.
Dimitrios Chasapis is a senior researcher in the Computer Sciences department at the Barcelona Supercomputing Center (BSC). His research focuses on the intersection of parallel programming models, runtime systems, and hardware architectures, with a particular emphasis on optimizing performance and efficiency in high-performance computing environments. He earned his Ph.D. from the Universitat Politècnica de Catalunya (UPC) in 2019, specializing in resource-aware computing for task-based runtimes on parallel architectures.
Throughout his career, Dr. Chasapis has worked extensively on mitigating the effects of hardware variability, designing intelligent runtime systems, and improving memory subsystem efficiency, including collaborative research on advanced prefetching and cache management strategies. His work utilizes sophisticated full-system simulators and development vehicles to evaluate next-generation processors. He has co-authored numerous papers in leading peer-reviewed venues, such as ACM Transactions on Architecture and Code Optimization (TACO) and the International Conference on Supercomputing (ICS).
Dr. Lluc Alvarez is a senior researcher within the Computer Sciences department at the Barcelona Supercomputing Center (BSC). His research centers on high-performance computer architecture, with a strong focus on runtime systems, task-based parallel programming models, and memory hierarchy optimization. He has been deeply involved in co-designing hardware-software interfaces to improve processor efficiency and scalability for next-generation supercomputers.
He earned his Ph.D. from the Universitat Politècnica de Catalunya (UPC), specializing in architectural support and runtime strategies for parallel systems. Over his career, Dr. Alvarez has contributed significantly to microarchitecture research, including work on memory subsystems, cache management, and hardware prefetching mechanisms. His research is widely published in top-tier computer architecture and high-performance computing venues, reflecting his active collaboration on cutting-edge systems at BSC.
Daniel A. Jiménez is a Professor in the Computer Science and Engineering Department at Texas A&M University. His research focuses on microarchitecture and the critical interaction between compilers and microarchitectural designs, with extensive work in branch prediction and cache management.
He is widely recognized for inventing the perceptron branch predictor. In recognition of his contributions to the field, he was elevated to IEEE Fellow in 2021 for his work in branch prediction. Most recently, he received the B. Ramakrishna Rau Award for his significant contributions to neural branch prediction in microprocessors.