Presented Enhancing Instruction Prefetching via Cache and TLB Management at ISCA 2026 in Raleigh, North Carolina, United States of America.
Earlier this week I headed out from Barcelona, Spain to Raleigh, NC, USA, to present Enhancing Instruction Prefetching via Cache and TLB Management at 53rd International Symposium on Computer Architecture (ISCA 2026).
The conference was an invigorating assembly of the leading minds in microarchitecture. It was a privilege to share our findings and engage in deep technical discussions with fellow researchers following the presentation.
Resources
- 📄 Paper: Download the full paper (PDF)
- 📊 Slides: Presentation Slides (PPTX)